This invention relates to memory testing, and more particularly, to configurable built in self test circuitry for performing memory tests.
Memory is widely used in the integrated circuit industry. Memory arrays are formed as part of integrated circuits such as application specific integrated circuits, programmable logic device integrated circuits, digital signal processors, microprocessors, microcontrollers, and memory chips.
Integrated circuits are generally tested before being sold. Testing can reveal memory faults that arise during device manufacturing. For example, testing may reveal that a particular memory array cell is stuck at a logical one value or that it is impossible to read data from a particular memory array cell. Identifying errors such as these allows integrated circuits to be repaired or discarded as appropriate.
It is often desirable to perform memory tests at normal clock speeds. Such tests, which are sometimes referred to as at-speed memory tests, may reveal faults that would otherwise not appear and therefore help to ensure that memory on an integrated circuit has been thoroughly tested.
In order to adequately test a memory array on an integrated circuit, it is often desirable to design the integrated circuit so that it incorporates internal testing circuitry. Such testing circuitry, which is sometimes referred to as built in self test circuitry can be used to perform at-speed tests on the memory array. If the tests indicate that a fault is present, the integrated circuit that contains the fault may be repaired or discarded.
In a typical configuration, a hardwired built in self test circuit is included on an integrated circuit. During testing, the hardwired built in self test circuit applies test vectors to the memory array to determine whether the memory array contains faults. If desired, a so-called soft built in self test circuit can be implemented from programmable logic resources on a programmable logic device integrated circuit.
Although hardwired and soft built in self test circuitry allows memory arrays to be tested at speed, the built in self test circuitry can consume a relatively large amount of circuit resources. This is particularly true when the built in self test circuitry is designed to run a number of different tests. For example, a built in self test circuit that has been designed to run five different memory tests might require roughly five times as much circuit real estate as a built in self test circuit that has been designed to run a single memory test.
It would therefore be desirable to be able to produce built in self test circuitry that can be configured to perform different memory tests without consuming significant amounts of circuit resources.